This is my MV/9800 PCB this example is the dual processor version (P/N 005-400190) there is also a single CPU version (P/N 005-400184). Interestingly the CPU(s) are stamped ‘Super Washi’. I recall reading somewhere that Washi was Japanese for Eagle, this makes sense given the MV’s birth (The first 32bit Eclipse) was code named Eagle internally at Data General. This PCB also has 2 x 32Mb Memory Boards fitted (P/N 005-035921); you will also note that it’s a very busy board with an incredible amount of VLSI used.
When you look at the complexity of this PCB compared to the sparseness of Mag Tape Controller (005-015289) you can see just how far DG progressed with PCB design, helped of course by the progression of Integrated Circuits and CAD technology (some of which DG machines powered!).
Launch Information
Announcing the MV/9800, a powerful, general purpose rackmount system or server.
The MV/9800 is available as either a single 14-MIPS or dual 28-MIPS system with support for up to 128 MB of ERCC memory, 624 asynchronous connects, and up to 400 GB of disk storage on the BMC.
Select high-end features such as ERCC memory, automatic de-configuration of failed components, autorestart, and enhanced on-board diagnostics maximize system uptime, protect your valuable data, and lower maintenance costs.
Technical Specification
The MV/9800 processors support Burst Multiplexer Channel (BMC), Data Channel (DCH), Programmed I/O (PIO) devices, and the Message-Based Reliable Channel (MRC). The MV/9800 processor is based on the WASHI 2.0 CPU with 2KB internal cache and 256 KB external cache.
The MV/9800 system PCB has:
- One BMC/DCH
- RTC/PIT and architectural clock
- COMSWITCH II remote diagnostics
- MRC
Memory is provided with 32 MB Error Checking and Correcting (ERCC) memory PCBs. Up to four memory PCBs can be connected to the system PCB for a maximum memory of 128 MB.
The MV/9800 supports:
- 128 MB memory
- 14 I/O controllers
- 8 BMC controllers
- 4 LAN controllers
- 2 MCA controllers
- 624 asynchronous lines
- 16 synchronous lines
- 2 expansion chassis
- AOS/VS CLASSIC and AOS/VS II operating systems
The MV/9800 meets the following performance specifications:
CPU Performance:
- 14 MIPS (1 processor), 28 MIPS (2 processors)
- Word size: 32-bits
- Instruction width: 16 – 80 bits
- Processor cycle time: 34 ns (33 MHz)
Data Transfer Rates:
- BMC input: 13.4 MB/sec
- BMC output: 13.2 MB/sec
- DCH input: 2.51 MB/sec
- DCH output: 1.37 MB/sec
Switch and Jumper Settings
Jumper J15 controls the CTS signal. Pins 2 and 3 shorted enables software flow control (XON/OFF) and pins 1 and 2 shorted enables hardware handshaking (CTS Asserted).
The System Console Baud Rate and Interface (RS232C or 20ma Current Loop) can be configured using by the following switches:
SW1-1,2,3,4 RS232C=1010
20ma=0111
SW1-5,6,7,8 19200=1110 4800=1100
9600=1101 2400=1010
The remaining ports on the CPU can be configured as follows:
IAC Port
SW2-1,2,3,4 + SW3-8: RS232C=1010+0 or RS422=0111+1
User Port
SW2-5,6,7,8 + SW3-7: RS232C=1010+0 or RS422=0111+1
The remaining MV/9800 Jumpers have the following default positions:
P-1 FRONT Three-pin
P-2 FRONT Three-pin
P-3 FRONT Three-pin
P-4 IN Two-pin
P-5 OUT Three-pin
P-6 FRONT Three-pin
P-7 FRONT Three-pin
P-8 OUT Three-pin
P-9 OUT Two-pin
P-10 FRONT Three-pin
P-11 FRONT Three-pin
P-12 OUT Three-pin
P-13 IN Two-pin
P-14 FRONT Three-pin
P-15 FRONT Three-pin
P-16 IN Two-pin
P-17 FRONT Three-pin
P-18 FRONT Three-pin
P-19 FRONT Three-pin
P-20 FRONT Three-pin
P-21 FRONT Three-pin
P-22 FRONT Three-pin
P-23 FRONT Three-pin
P-24 FRONT Three-pin
P-25 FRONT Three-pin
P-26 FRONT Three-pin
P-27 FRONT Three-pin
P-28 FRONT Three-pin
P-29 FRONT Three-pin
P-30 FRONT Three-pin
P-31 FRONT Three-pin
P-32 OUT Two-pin
P-33 IN Two-pin
P-34 FRONT Three-pin
P-35 FRONT Three-pin
P-36 FRONT Three-pin
P-37 FRONT Three-pin
P-38 FRONT Three-pin
P-39 OUT Two-pin
P-40 FRONT Three-pin
P-41 IN Two-pin
Power Up Self Test
On system Power Up the MV/9800 conducts a series of tests to ensure it is able to function correctly. These are represented in the following letters that are written to the System Console:
MV/System Power Up Testing Completed
Should the full message not be displayed you can use the table below to identify at which point the self test has failed:
M PROM Checksum Test V Reserved / Reserved S Non-volatile RAM test y Asynchronous Serial Interface Test s Scan Loopback Test t Initial System Shutup e SBUS Interface Initialization m JP Start Address Unit Test space Reserved P System Sizing o Boot Clock Test w Memory System Power up e State Page Setup r I/O Channel Tests space Reserved U Device Code Tests p Job Processor Tests space Reserved T Multi-Processor Tests e RNB Loopback Test s Reserved t Reserved i Reserved n Reserved g Reserved space Reserved C Reserved o Reserved m Reserved p Reserved l Reserved e Reserved t Reserved e Reserved d Enable Error Detection
Related Documentation
043-003644 – Installation, Repair and Maintenance Eclipse MV/9800 Series
043-000102 – Product Service Guide
015-000916 – Site Planning Guide
015-000355 – MV Remote Assistance User Guide
014-002393 – Starting, Operating, and Configuring an MV/9800 Series Computer System
014-001856 – Designing Interfaces for the ECLIPSE I/O Bus
014-001186 – CORESIDENT Diagnostics System Operators Guide
014-001280 – CORESIDENT ADEX User’s Manual
052-000197 – CORESIDENT ADEX SPI
043-000086 – Field Guide for the ECLIPSE MV Proprietary Diagnostic Password System
043-000072 – How to Use MVSYSTEMX
014-000744 – ADEX Operator’s Manual
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